| Manufacturer | Part # | Datasheet | Description |
Cypress Semiconductor
|
CY14B104K |
1Mb/34P |
4-Mbit (512 K 횞 8/256 K 횞 16) nvSRAM with Real Time Clock |
| CY7C1146V18 |
1Mb/27P |
18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1266V18 |
1Mb/27P |
36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1566KV18 |
921Kb/31P |
72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY22150 |
211Kb/13P |
One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator |
| CY8CMBR3002 |
1Mb/42P |
CapSense짰 Express??Controllers with SmartSense??Auto-tuning 16 Buttons, 2 Sliders, Proximity Sensors |
| CY14B104K |
1Mb/33P |
4-Mbit (512 K 횞 8/256 K 횞 16) nvSRAM with Real Time Clock |
| CY14B116K |
1Mb/42P |
16-Mbit (2048 K 횞 8/1024 K 횞 16) nvSRAM with Real Time Clock |
| CY7C1246V18 |
1Mb/27P |
36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1546KV18 |
959Kb/31P |
72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CYF1018V |
921Kb/28P |
18/36/72-Mbit Programmable 2-Queue FIFOs Independent read and write ports |
| CY7C12461KV18 |
895Kb/29P |
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1266KV18 |
919Kb/28P |
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1566V18 |
664Kb/28P |
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1166V18 |
1Mb/27P |
18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C12661KV18 |
903Kb/30P |
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1546V18 |
1Mb/27P |
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1566V18 |
1Mb/27P |
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1480BV33 |
1,015Kb/33P |
72-Mbit (2 M 횞 36/4 M 횞 18) Pipelined Sync SRAM |
| CY7C11461KV18 |
854Kb/29P |
18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
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