1. General description
The 74LVT08 is a quad 2-input AND gate. This device is fully specified for partial power down
applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging
backflow current through the device when it is powered down.
2. Features and benefits
• Wide supply voltage range from 2.7 V to 3.6 V
• Overvoltage tolerant inputs to 5.5 V
• BiCMOS high speed and output drive
• Output capability: +64 mA and -32 mA
• Direct interface with TTL levels
• No bus current loading when output is tied to 5 V bus
• Power-up 3-state
• IOFF circuitry provides partial Power-down mode operation
• Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
• Complies with JEDEC standard: JESD8C (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114E exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Specified from -40 °C to 85 °C