DSP56857 datasheet(243/662 Pages) FREESCALE

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Functional Description

Serial Communications Interface (SCI), Rev. 4

Freescale Semiconductor

10-7

10.6.2 Baud Rate Generation

A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver

and the transmitter. A value of 1 to 8191 written to the SBR bits determines the module clock

divisor. A value of zero disables the baud rate generator. The SBR bits are bits 12:0 of the SCI

Baud Rate (SCIBR) register. The baud rate clock is synchronized with the bus clock, driving the

receiver. The baud rate clock, divided by 16, drives the transmitter. The receiver has an

acquisition rate of 16 samples per bit time.

Baud rate generation is subject to two sources of error:

1. Integer division of the module clock may not give the exact target frequency.

2. Synchronization with the bus clock can cause phase shift.

Table 10-6 lists examples of achieving target baud rates with a module clock frequency of

60MHz.

Note:

Maximum baud rate is module clock rate, divided by 16. System overhead may

preclude processing the data at this speed.

Table 10-5. Example 9-Bit Data Frame Formats

Start

Bit

Data

Bits

Address

Bit

Parity

Bit

Stop

Bit

19001

18002

18011

1. The address bit identifies the frame as an address character.

Please see Section 10.6.4.8

Table 10-6. Example Baud Rates (Module Clock = 60MHz)

SBR

Bits

Receiver Clock

(Hz)

Transmitter Clock

(Hz)

Target Baud

Rate

Error (%)

612245

38265

38,400

-0.35

195

307692

19231

19,200

0.16

391

153453

9591

9600

-0.09

781

76825

4802

4800

0.04

1563

38388

2399

2400

-0.04

3125

19200

1200

0.00

6250

9600

600

0.00

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