DSP56857 datasheet(352/662 Pages) FREESCALE

352 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

12-52

Freescale Semiconductor

12.8.11.4 Prescaler Modulus Select (PM)—Bits 7–0

This bit field specifies the divide ratio of the prescale divider in the ESSI clock generator. This

prescaler is used only in Internal Clock mode to divide the internal peripheral clock. A divide

ratio from 1 to 256 (PM = $00 to $FF) can be selected. The bit clock output is available at the

SCK or SC0 clock pins. The bit clock on the ESSI can be calculated from the peripheral clock

value using the following equation:

fFIX_CLK = fIPBus_CLK/4

if DIV4DIS = 0

fFIX_CLK = fIPBus_CLK

if DIV4DIS = 1

fINT_BIT_CLK = fFIX_CLK /[4 x (7 x PSR + 1) x (PM + 1)]

fFRAME_SYN_CLK = (fINT_BIT_CLK)/[(DC + 1) x WL] where DC = DC and WL = 8, 10, 12,

or 16

For example if an 8kHz sampling rate is desired, with 8-bit words operating in the Normal mode,

the following parameters can be used:

fIPBus_CLK = fSYSTEM_CLK /2 = 120MHz / = 60mhz

fFIX_CLK = fIPBus_CLK = 60MHz DIV4DIS = 1

fINT_BIT_CLK = fFIX_CLK /[4 x(7 x PSR + 1)x(PM + 1)]

= 60 MHz /[4 x 1 x 117] = 128.2kHz

PS = 0, PM = 116

fFRAME_SYN_CLK = (fINT_BIT_CLK)/[(DC + 1) x WL] DC = 1 = 128kHz/[2 x 8]

= 8.012kHz

The bit clock output is also available internally for use as the bit clock to shift the Transmit and

Receive Shift registers. Careful choice of the crystal oscillator frequency and the prescaler

modulus provides the telecommunication industry standard codec master clock frequencies of

2.048MHz and 1.536MHz to be generated; however, such applications will typically use external

clocks and frame syncs. Table 12-18 provides examples of PM, PSR, and DIV4DIS values

available to be used to generate different bit clocks.

DSP56857 Datasheet(PDF) 352 Page - Freescale Semiconductor, Inc