PIC18F4520ESLASHMLQTP datasheet(265/390 Pages) MICROCHIP

265 / 390 page

 2004 Microchip Technology Inc.

Preliminary

DS39631A-page 263

PIC18F2420/2520/4420/4520

23.5

Program Verification and

Code Protection

The overall structure of the code protection on the

PIC18 Flash devices differs significantly from other

PICmicro® devices.

The user program memory is divided into five blocks.

One of these is a boot block of 2 Kbytes. The remainder

of the memory is divided into four blocks on binary

boundaries.

Each of the five blocks has three code protection bits

associated with them. They are:

• Code-Protect bit (CPn)

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 23-5 shows the program memory organization

for 16 and 32-Kbyte devices and the specific code pro-

tection bit associated with each block. The actual

locations of the bits are summarized in Table 23-3.

FIGURE 23-5:

CODE-PROTECTED PROGRAM MEMORY FOR

PIC18F2420/2520/4420/4520

TABLE 23-3:

SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h

CONFIG5L

—

—CP3(1,2)

CP2(1)

CP1

CP0

300009h

CONFIG5H

CPD

CPB

—

30000Ah

CONFIG6L

—

—WRT3(1,2)

WRT2(1)

WRT1

WRT0

30000Bh

CONFIG6H

WRTD

WRTB

WRTC

—

30000Ch

CONFIG7L

—

EBTR3(1,2)

EBTR2(1)

EBTR1

EBTR0

30000Dh

CONFIG7H

—

EBTRB

—

Legend: Shaded cells are unimplemented.

Note 1:

Unimplemented in PIC18F2420/4420 devices; maintain this bit set.

Unimplemented in PIC18F2425/4425 devices; maintain this bit set.

MEMORY SIZE/DEVICE

Block Code Protection

Controlled By:

16 Kbytes

(PIC18F2420/4420)

32 Kbytes

(PIC18F2520/4520)

Address

Range

Boot Block

000000h

0007FFh

CPB, WRTB, EBTRB

Block 0

000800h

001FFFh

CP0, WRT0, EBTR0

Block 1

002000h

003FFFh

CP1, WRT1, EBTR1

Unimplemented

Read ‘0’s

Block 2

004000h

005FFFh

CP2, WRT2, EBTR2

Block 3

006000h

007FFFh

CP3, WRT3, EBTR3

Unimplemented

Read ‘0’s

1FFFFFh

(Unimplemented Memory Space)

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