PIC18F4520ESLASHMLQTP datasheet(282/390 Pages) MICROCHIP

282 / 390 page

PIC18F2420/2520/4420/4520

DS39631A-page 280

Preliminary

 2004 Microchip Technology Inc.

BTFSC

Bit Test File, Skip if Clear

Syntax:

BTFSC f, b {,a}

Operands:

≤ f ≤ 255

≤ b ≤ 7

∈ [0,1]

Operation:

skip if (f<b>) = 0

Status Affected:

None

Encoding:

1011

bbba

ffff

Description:

If bit ‘b’ in register ‘f’ is ‘0’, then the next

instruction is skipped. If bit ‘b’ is ‘0’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOP is executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates in

Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh).

See Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1(2)

Note:

3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

operation

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE

FALSE

TRUE

BTFSC

FLAG, 1, 0

Before Instruction

address (HERE)

After Instruction

If FLAG<1>

address (TRUE)

If FLAG<1>

address (FALSE)

BTFSS

Bit Test File, Skip if Set

Syntax:

BTFSS f, b {,a}

Operands:

≤ f ≤ 255

≤ b < 7

∈ [0,1]

Operation:

skip if (f<b>) = 1

Status Affected:

None

Encoding:

1010

bbba

ffff

Description:

If bit ‘b’ in register ‘f’ is ‘1’, then the next

instruction is skipped. If bit ‘b’ is ‘1’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOP is executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh).

See Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1(2)

Note:

3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

operation

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE

FALSE

TRUE

BTFSS

FLAG, 1, 0

Before Instruction

address (HERE)

After Instruction

If FLAG<1>

address (FALSE)

If FLAG<1>

address (TRUE)

PIC18F4520E/MLQTP Datasheet(PDF) 282 Page - Microchip Technology

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