PIC18F4520ESLASHMLQTP datasheet(358/390 Pages) MICROCHIP

358 / 390 page

PIC18F2420/2520/4420/4520

DS39631A-page 356

Preliminary

 2004 Microchip Technology Inc.

TABLE 26-21: MASTER SSP I2C BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min

Max

Units

Conditions

100

THIGH

Clock High Time 100 kHz mode

2(TOSC)(BRG + 1)

—

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

101

TLOW

Clock Low Time

100 kHz mode

2(TOSC)(BRG + 1)

—

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

102

SDA and SCL

Rise Time

100 kHz mode

—

1000

CB is specified to be from

10 to 400 pF

400 kHz mode

20 + 0.1 CB

300

1 MHz mode(1)

—

300

103

SDA and SCL

Fall Time

100 kHz mode

—

300

CB is specified to be from

10 to 400 pF

400 kHz mode

20 + 0.1 CB

300

1 MHz mode(1)

—

100

TSU:STA

Start Condition

Setup Time

100 kHz mode

2(TOSC)(BRG + 1)

—

Only relevant for

Repeated Start

condition

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

THD:STA Start Condition

Hold Time

100 kHz mode

2(TOSC)(BRG + 1)

—

After this period, the first

clock pulse is generated

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

106

THD:DAT Data Input

Hold Time

100 kHz mode

—

400 kHz mode

0.9

107

TSU:DAT

Data Input

Setup Time

100 kHz mode

250

—

(Note 2)

400 kHz mode

100

—

TSU:STO

Stop Condition

Setup Time

100 kHz mode

2(TOSC)(BRG + 1)

—

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

109

TAA

Output Valid

from Clock

100 kHz mode

—

3500

400 kHz mode

—

1000

1 MHz mode(1)

——

110

TBUF

Bus Free Time

100 kHz mode

4.7

—

Time the bus must be free

before a new transmission

can start

400 kHz mode

1.3

—

D102

Bus Capacitive Loading

—

400

Note 1:

Maximum pin capacitance = 10 pF for all I2C pins.

A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter 107

≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit

to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the

SCL line is released.

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