PIC18F4520ESLASHMLQTP datasheet(137/390 Pages) MICROCHIP

137 / 390 page

 2004 Microchip Technology Inc.

Preliminary

DS39631A-page 135

PIC18F2420/2520/4420/4520

14.0

TIMER3 MODULE

The Timer3 module timer/counter incorporates these

features:

• Software selectable operation as a 16-bit timer or

counter

• Readable and writable 8-bit registers (TMR3H

and TMR3L)

• Selectable clock source (internal or external) with

device clock or Timer1 oscillator internal options

• Interrupt-on-overflow

• Module Reset on CCP Special Event Trigger

A simplified block diagram of the Timer3 module is

shown in Figure 14-1. A block diagram of the module’s

operation in Read/Write mode is shown in Figure 14-2.

The Timer3 module is controlled through the T3CON

options for the CCP modules (see Section 15.1.1

“CCP Modules and Timer Resources” for more

information).

T3CON: TIMER3 CONTROL REGISTER

R/W-0

RD16

T3CCP2

T3CKPS1

T3CKPS0

T3CCP1

T3SYNC

TMR3CS

TMR3ON

bit 7

bit 0

bit 7

RD16: 16-bit Read/Write Mode Enable bit

= Enables register read/write of Timer3 in one 16-bit operation

= Enables register read/write of Timer3 in two 8-bit operations

bit 6,3

T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits

= Timer3 is the capture/compare clock source for the CCP modules

= Timer3 is the capture/compare clock source for CCP2;

Timer1 is the capture/compare clock source for CCP1

= Timer1 is the capture/compare clock source for the CCP modules

bit 5-4

T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits

= 1:8 Prescale value

= 1:4 Prescale value

= 1:2 Prescale value

= 1:1 Prescale value

bit 2

T3SYNC: Timer3 External Clock Input Synchronization Control bit

(Not usable if the device clock comes from Timer1/Timer3.)

When TMR3CS = 1:

= Do not synchronize external clock input

= Synchronize external clock input

When TMR3CS = 0:

This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1

TMR3CS: Timer3 Clock Source Select bit

= External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first

falling edge)

= Internal clock (FOSC/4)

bit 0

TMR3ON: Timer3 On bit

= Enables Timer3

= Stops Timer3

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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