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AR8327-AL1A-R Datasheet(PDF) 354 Page - List of Unclassifed Manufacturers |
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AR8327-AL1A-R Datasheet(HTML) 354 Page - List of Unclassifed Manufacturers |
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354 / 394 page  354 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc. 354 • June 2011 COMPANY CONFIDENTIAL 3.10.10 1000Base-T Control Register Address Offset: 0x09, or 0d09 Table 3-375, “1000Base-T Control Register Register,” on page 354 summarizes the Register Table 3-375. 1000Base-T Control Register Register 13 Message Page Mode Mode RO Received Code Word Bit 13 HW Rst 0 SW Rst 0 12 Ack2 Mode RO Received Code Word Bit 12 HW Rst 0 SW Rst 0 11 Toggle Mode RO Received Code Word Bit 11 HW Rst 0 SW Rst 0 10:0 Message/ Unformatted Field Mode R/W Received Code Word Bit 10:0 HW Rst 0x000 SW Rst 0x000 Bit Symbol Type Description Bit Symbol Type Description 15:13 Test Mode Mode R/W TX_TCLK comes from the RX_CLK pin for jitter testing in test modes 2 and 3. After exiting the test mode, hardware reset or software reset (register 0.15) should be issued to ensure normal operation. 000 = Normal Mode 001 = Test Mode 1 - Transmit Waveform Test 010 = Test Mode 2 - Transmit Jitter Test (MASTER mode) 011 = Test Mode 3 - Transmit Jitter Test (SLAVE mode) 100 = Test Mode 4 - Transmit Distortion Test 101, 110, 111 = Reserved HW Rst 000 SW Rst Retain 12 Master/Slave manual Configuratio n Enable Mode R/W The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down 1 = Manual MASTER/SLAVE configuration 0 = Automatic MASTER/SLAVE configuration HW Rst 0 SW Rst Update |
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