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STM32L4A6VG Datasheet(PDF) 220 Page - STMicroelectronics |
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STM32L4A6VG Datasheet(HTML) 220 Page - STMicroelectronics |
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220 / 282 page  Electrical characteristics STM32L4A6xG 220/282 DS11584 Rev 8 Figure 38. SPI timing diagram - slave mode and CPHA = 0 tv(SO) Data output valid time Slave mode 2.7 V < VDD < 3.6 V Voltage Range 1 -13 15.5 ns Slave mode 1.71 V < VDD < 3.6 V Voltage Range 1 -13 26.5 Slave mode 1.71 V < VDD < 3.6 V Voltage Range 2 -13 30 - Slave mode 1.08 V < VDDIO2 < 1.32 V(3) -26 60 tv(MO) Master mode - 4.5 6 th(SO) Data output hold time Slave mode 1.71 V < VDD < 3.6 V 7 - - th(MO) Master mode 0 - - 1. Guaranteed by characterization results. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50 %. 3. SPI mapped on Port G. Table 96. SPI characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit |
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