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STM32L4A6VG Datasheet(PDF) 238 Page - STMicroelectronics |
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STM32L4A6VG Datasheet(HTML) 238 Page - STMicroelectronics |
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238 / 282 page  Electrical characteristics STM32L4A6xG 238/282 DS11584 Rev 8 Figure 51. Asynchronous multiplexed PSRAM/NOR write waveforms Table 111. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 4THCLK-1 4THCLK+1 ns tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK-1 THCLK+1 tw(NWE) FMC_NWE low time 2xTHCLK-0.5 2xTHCLK+ 0.5 th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK-0.5 - tv(A_NE) FMC_NEx low to FMC_A valid - 0 tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5 tw(NADV) FMC_NADV low time THCLK THCLK+1 th(AD_NADV) FMC_AD(adress) valid hold time after FMC_NADV high THCLK+ 0.5 - th(A_NWE) Address hold time after FMC_NWE high THCLK+ 0.5 - th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK- 0.5 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 tv(Data_NADV) FMC_NADV high to Data valid - THCLK +3 th(Data_NWE) Data hold time after FMC_NWE high THCLK +0.5 - |
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