LPC47M14X datasheet(133/205 Pages) SMSC

133 / 205 page

SMSC DS – LPC47M14X

Page 133

Rev. 03/19/2001

NAME

REG OFFSET

(hex)

DESCRIPTION

SMI_STS3

Default = 0x00

on VTR POR

(R/W)

SMI Status Register 3

This register is used to read the status of the SMI inputs.

The following bits are cleared on a write of ‘1’.

Bit[0] GP20

Bit[1] GP21

Bit[2] GP22

Bit[3] Reserved

Bit[4] GP24

Bit[5] GP25

Bit[6] GP26

Bit[7] GP60

SMI_STS4

Default = 0x00

on VTR POR

(Note 6)

(R/W)

SMI Status Register 4

This register is used to read the status of the SMI inputs.

The following bits are cleared on a write of ‘1’.

Bit[0] GP30

Bit[1] GP31

Bit[2] GP32

Bit[3] GP33

Bit[4] GP41

Bit[5] GP42

Bit[6] GP43

Bit[7] GP61

SMI_STS5

Default = 0x00

on VTR POR

(R/W)

SMI Status Register 5

This register is used to read the status of the SMI inputs.

The following bits are cleared on a write of ‘1’.

Bit[0] GP54

Bit[1] GP55

Bit[2] GP56

Bit[3] GP57

Bit[4] Reserved

Bit[5] Reserved

Bit[6] FAN_TACH1

Bit[7] FAN_TACH2

N/A

(R)

Reserved – reads return 0

SMI_EN1

Default = 0x00

on VTR POR

(R/W)

SMI Enable Register 1

This register is used to enable the different interrupt

sources onto the group nSMI output.

1=Enable

0=Disable

Bit[0] Reserved

Bit[1] EN_PINT

Bit[2] EN_U2INT

Bit[3] EN_U1INT

Bit[4] EN_FINT

Bit[5] EN_MPU-401 INT

Bit[6] Reserved

Bit[7] Reserved (Note 7)

LPC47M14X Datasheet(PDF) 133 Page - SMSC Corporation

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