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LPC47M14X Datasheet(PDF) 152 Page - SMSC Corporation |
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LPC47M14X Datasheet(HTML) 152 Page - SMSC Corporation |
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152 / 205 page ![]() SMSC DS – LPC47M14X Page 152 Rev. 03/19/2001 8 CONFIGURATION The Configuration of the LPC47M14x is very flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The LPC47M14x is designed for motherboard applications in which the resources required by their components are known. With its flexible resource allocation architecture, the LPC47M14x allows the BIOS to assign resources at POST. SYSTEM ELEMENTS Primary Configuration Address Decoder After a hard reset (PCI_RESET# pin asserted) or Vcc Power On Reset the LPC47M14x is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the LPC47M14x into Configuration Mode. The BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and DATA ports are only valid when the LPC47M14x is in Configuration Mode. The SYSOPT pin is latched on the falling edge of the PCI_RESET# or on Vcc Power On Reset to determine the configuration register's base address. The SYSOPT pin is used to select the CONFIG PORT's I/O address at power-up. Once powered up the configuration port base address can be changed through configuration registers CR26 and CR27. The SYSOPT pin is a hardware configuration pin which is shared with the GP24 signal on pin 45. Note: An external pull-down resistor is required for the base IO address to be 0x02E for configuration. An external pull-up resistor is required to move the base IO address for configuration to 0x04E. The INDEX and DATA ports are effective only when the chip is in the Configuration State. PORT NAME SYSOPT= 0 10k PULL-DOWN RESISTOR SYSOPT= 1 10K PULL-UP RESISTOR TYPE CONFIG PORT (Note) 0x02E 0x04E Write INDEX PORT (Note) 0x02E 0x04E Read/Write DATA PORT INDEX PORT + 1 Read/Write Note : The configuration port base address can be relocated through CR26 and CR27. Entering the Configuration State The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = <0x55> Exiting the Configuration State The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = <0xAA> |
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