UPD360 datasheet(155/221 Pages) MICROCHIP

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 2016-2017 Microchip Technology Inc.

DS00002084C-page 155

UPD360

11.4.3.3

RX Interrupt Status Register (RX_IRQ_STAT)

This register reflects the status of various RX_IRQ_STAT sources. Whether an interrupt is generated or not depends on

the values in the RX Interrupt Enable Register (RX_IRQ_EN).

Bits in this register are set by hardware and must be cleared by software.

TX_FAILED

Applicable in Auto Retry Mode only (or when GoodCRC timer is enabled).

This interrupt indicates a TX message request failed to complete for one of

the following reasons:

• GoodCRC timer expired

• Maximum number of retries exceeded

Note:

Software may enable the GoodCRC timer without enabling Auto

Retry. In this case this interrupt will be generated when GoodCRC

timer expires. It is software's responsibility to disable the Good-

CRC timer on reception of GoodCRC message to prevent genera-

tion of this interrupt.

R/W1C

TX_DONE

Applicable in Auto Retry Mode only. A TX message request is successfully

completed, i.e., the message is acknowledged with GoodCRC by recipient.

This bit is not set for messages that don't get a GoodCRC message, i.e., Hard

or Cable Reset. TX_EOP should be used in such situations.

When Auto Retry Mode is disabled, TX_EOP should be used to determine

when packet is done transmitting.

R/W1C

Address:

1A82h

Size:

8 bits

Bits

Description

Type

Default

RX_FIFO_NOT_EMPTY

RX FIFO is not empty. This bit is set whenever the RX FIFO has data to be

read. Typically set when a valid packet is finished being received and cleared

once all data has been read.

Note:

This bit is read only and is cleared once the FIFO is empty.

LINE_WENT_IDLE

Line is now idle. This bit is set when hardware detects no activity on the PD

bus.

Note:

This bit is not line status, it is an event. If line is already idle when

this interrupt is enabled, this bit will be set immediately. If line is

busy when this interrupt is enabled, this bit will be set when line

goes idle.

Software can use this to be informed when either TX is over or RX is over.

This will only work while clocks are enabled.

R/W1C

RX_CABLE_RST

Cable Reset Message received.

R/W1C

RESERVED

RX_HARD_RST

Hard Reset Message received.

R/W1C

Bits

Description

Type

Default

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