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STM32G474PBY3XXX Datasheet(PDF) 153 Page - STMicroelectronics |
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STM32G474PBY3XXX Datasheet(HTML) 153 Page - STMicroelectronics |
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153 / 236 page  DS12288 Rev 5 153/236 STM32G474xB STM32G474xC STM32G474xE Electrical characteristics 200 Figure 28. ADC accuracy characteristics Figure 29. Typical connection diagram using the ADC 1. Refer to Table 66: ADC characteristics for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 54: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 3. Refer to Table 54: I/O static characteristics for the values of Ilkg. General PCB design guidelines Power supply decoupling must be performed as shown in Figure 16: Power supply scheme. The decoupling capacitor on VDDA must be ceramic (good quality) and it must be placed as close as possible to the chip. (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4095 4094 4093 7 6 5 4 3 2 1 0 2 3 4 5 6 4093 4094 4095 4096 ADC code 1 LSB IDEAL MS60205V1 Vin/VREF*4096 ED EL EG ET EO 17 (1) (3) (2) = total unajusted error: maximum deviation between the actual and ideal transfer curves. ET EO = offset error: maximum deviation between the first actual transition and the first ideal one. EG = gain error: deviation between the last ideal transition and the last actual one. = differential linearity error: maximum deviation between actual steps and the ideal ones. ED EL = integral linearity error: maximum deviation between any actual transition and the end point correlation line. MS33900V6 Sample and hold ADC converter 12-bit converter Cparasitic (2) Ilkg (3) CADC VDDA RAIN (1) VAIN AINx RADC |
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