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STM32MP157F Datasheet(PDF) 176 Page - STMicroelectronics

Part # STM32MP157F
Description  Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analog, crypto
PDF  260 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32MP157F Datasheet(HTML) 176 Page - STMicroelectronics

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Electrical characteristics
STM32MP157C/F
176/260
DS12505 Rev 5
Figure 24. Recommended NRST and NRST_CORE pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST/NRST_CORE pin can go below the VIL(NRST) max level
specified in Table 58. Otherwise the reset is not taken into account by the device.
6.3.19
FMC characteristics
Unless otherwise specified, the parameters given in Table 59 to Table 72 for the FMC
interface are derived from tests performed under the ambient temperature, Fmc_hclk (Fhclk6)
frequency and VDD supply voltage conditions summarized in Table 13: General operating
conditions, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Measurement points are done at CMOS levels: 0.5×VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Table 58. NRST and NRST_CORE pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU(2)
Weak pull-up equivalent
resistor(1)
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).
VIN = VSS
30
40
50
kΩ
VF(NRST)(2)
2. Guaranteed by design.
NRST/NRST_CORE Input
filtered pulse
1.71 V < VDD < 3.6 V
-
-
50
ns
VNF(NRST)(2)
NRST/NRST_CORE Input
not filtered pulse
1.71 V < VDD < 3.6 V
350
-
-
ai14132d
STM32
RPU
NRST(2)
VDD
Filter
Internal Reset
0.1 μF
External
reset circuit (1)



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