STM32MP157C datasheet(212/260 Pages) STMICROELECTRONICS

212 / 260 page

Electrical characteristics

STM32MP157C/F

212/260

DS12505 Rev 5

Table 92. DFSDM measured timing

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fDFSDMCLK

DFSDM clock

1.71 V < VDD < 3.6 V

fSYSCLK

MHz

fCKIN

(1/TCKIN)

Input clock

frequency

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 V < VDD < 3.6 V

(fDFSDMCLK/4)

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

2.7 < VDD < 3.6 V

(fDFSDMCLK/4)

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0]

≠0),

1.71 < VDD < 3.6 V

(fDFSDMCLK/4)

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0]

≠0),

2.7 < VDD < 3.6 V

(fDFSDMCLK/4)

fCKOUT

Output clock

frequency

1.71 < VDD < 3.6 V

DuCyCKOUT

Output clock

frequency duty

cycle

1.71 < VDD < 3.6 V

twh(CKIN)

twl(CKIN)

Input clock high

and low time

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < VDD < 3.6 V

TCKIN/2 - 0.5

TCKIN/2

tsu

Data input setup

time

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < VDD < 3.6 V

Data input hold

time

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < VDD < 3.6 V

0.5

TManchester

Manchester data

period (recovered

clock period)

Manchester mode

(SITP[1:0]=2,3),

Internal clock mode

(SPICKSEL[1:0]

¹0),

1.71 < VDD < 3.6 V

(CKOUTDIV+1)

×TDFSDMCLK(1)

(2×CKOUTDIV)

× TDFSDMCLK(1)

1. See DFSDM section in RM0436 reference manual for definition of CKOUTDIV.

STM32MP157C Datasheet(PDF) 212 Page - STMicroelectronics

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