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STM32L552CCT3PTR Datasheet(PDF) 288 Page - STMicroelectronics

Part # STM32L552CCT3PTR
Description  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU, 165 DMIPS, up to 512 KB Flash memory, 256 KB SRAM, SMPS
PDF  340 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L552CCT3PTR Datasheet(HTML) 288 Page - STMicroelectronics

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Electrical characteristics
STM32L552xx
288/340
DS12737 Rev 6
Table 140. Synchronous multiplexed NOR/PSRAM read timings(1)(2)
1. Guaranteed by characterization results, not tested in production.
2. Clock ratio R = (HCLK period /FMC_CLK period).
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
R*THCLK-0.5(2))
-
ns
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
-
2.5
td(CLKH_NExH)
FMC_CLK high to FMC_NEx high (x= 0…2)
R*THCLK/2+1(2)
-
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
2.5
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
2
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
-
5.5
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x=16…25)
R*THCLK/2 + 1(2)
-
td(CLKL-NOEL)
FMC_CLK low to FMC_NOE low
-
2
td(CLKH-NOEH)
FMC_CLK high to FMC_NOE high
R*THCLK/2+1(2)
-
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
3
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid
0
-
tsu(ADV-CLKH)
FMC_A/D[15:0] valid data before FMC_CLK
high
2-
th(CLKH-ADV)
FMC_A/D[15:0] valid data after FMC_CLK
high
4-
tsu(NWAIT-
CLKH)
FMC_NWAIT valid before FMC_CLK high
1.5
-
th(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high
4
-



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