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STM32WL55JC Datasheet(PDF) 115 Page - STMicroelectronics |
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STM32WL55JC Datasheet(HTML) 115 Page - STMicroelectronics |
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115 / 145 page  DS13293 Rev 1 115/145 STM32WL55/54xx Electrical characteristics 135 Figure 21. Recommended NRST pin protection 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in the above table. Otherwise the reset is not be taken into account by the device. 3. The external capacitor on NRST must be placed as close as possible to the device. 5.3.18 Analog switches booster Table 78. NRST pin characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) NRST input low level voltage - - - 0.3 x VDD V VIH(NRST) NRST input high level voltage - 0.7 x VDD -- Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV RPU Weak pull-up equivalent resistor(2) VIN = VSS 25 40 55 kΩ VF(NRST) NRST input, filtered pulse - - - 70 ns VNF(NRST) NRST input, not filtered pulse 1.8 V ≤ VDD ≤ 3.6 V 350 - - 1. Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10 %) . MS19878V3 RPU VDD Internal reset External reset circuit (1) NRST (2) Filter 0.1 μF Table 79. Analog switches booster characteristics(1) Symbol Parameter Min Typ Max Unit VDD Supply voltage 1.8 - 3.6 V tSU(BOOST) Booster startup time - - 240 µs IDD(BOOST) Booster consumption for 1.8 V ≤ VDD ≤ 2.0 V - - 250 µA Booster consumption for 2.0 V ≤ VDD ≤ 2.7 V - - 500 Booster consumption for 2.7 V ≤ VDD ≤ 3.6 V - - 900 1. Guaranteed by design. |
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