AM6548 datasheet(224/282 Pages) TI

224 / 282 page

NO.

DESCRIPTION(1)

MODE

MIN

MAX

UNIT

O10 td(CLK-CSn)

Delay time, CLK rising edge to CSn active edge

1.8V

0.475 × P +

0.975 × N × R

- 1(1) (2) (4)

0.475 × P +

0.975 × N × R

+ 1 (1) (2) (4)

3.3V

0.475 × P +

0.975 × N × R

- 1(1) (2) (4)

0.475 × P +

0.975 × N × R

+ 1 (1) (2) (4)

O11 td(CLK-CSn)

Delay time, CLK rising edge to CSn inactive

edge

1.8V

0.475 × P +

0.975 × N × R

- 1 (1) (3) (4)

0.475 × P +

0.975 × N × R

(1) (3) (4)

3.3V

0.475 × P +

0.975 × N × R

- 1(1) (3) (4)

0.475 × P +

0.975 × N × R

+ 1 (1) (3) (4)

O12 td(CLK-D)

Delay time, CLK active edge to D[i:0] transition

1.8V

-1.15

1.25

3.3V

-1.33

1.51

(1)

P = CLK cycle time = SCLK period

(2)

N = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = refclk

OSPI_CLK

OSPI_D[i:0]

OSPI_TIMING_02

OSPI_CSn

O10

O11

O12

Figure 7-88. OSPI Switching Characteristics - SDR

Section 7.9.5.18.2.3, Section 7.9.5.18.2.1, Figure 7-89, and Figure 7-87 presents timing requirements for OSPI

DDR and SDR Mode.

7.9.5.18.2.3 OSPI Timing Requirements - DDR Mode

Table 7-68. OSPI DLL Delay Mapping - DDR Timing Modes

OSPI Instance

MODE

OSPI_PHY_CONFIGURATION_REG BIT

FIELD

DELAY VALUE

OSPI0

1.8V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x41

3.3V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x46

1.8V DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x16

3.3V DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x3E

Non-PHY mode

PHY_CONFIG_RX_DLL_DELAY_FLD

0x0

OSPI1

1.8V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x44

3.3V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x4C

1.8V DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x16

3.3V DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x40

Non-PHY mode

PHY_CONFIG_RX_DLL_DELAY_FLD

0x0

AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

www.ti.com

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