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7.9.5.21.1.3.2 PRU_ICSSG PRU Switching Characteristics - Shift Out Mode

NO.

PARAMETER

MIN

MAX

UNIT

PRSO1

tc(CLKOUT)

Cycle time, CLKOUT

PRSO2

tw(CLKOUTL)

Pulse Duration, CLKOUT Low

-0.3 +

0.475×P×Z

(1) (2)

PRSO3

tw(CLKOUTH)

Pulse Duration, CLKOUT High

-0.3 +

0.475×P×Y

(1) (3)

PRSO4

td(CLKOUT-DATAOUT)

Delay time, CLKOUT to DATAOUT Valid

-1

(1)

P = Software programmable shift out clock period, defined by PRU0_GPO_DIV0 and PRU0_GPO_DIV1 bit fields in the GPCFGn

(2)

The Z parameter is defined as follows: If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are INTEGERS -or- if PRU0_GPI_DIV0 is a NON-

INTEGER and PRU0_GPI_DIV1 is an EVEN INTEGER then, Z equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1). If PRU0_GPI_DIV0

is a NON-INTEGER and PRU0_GPI_DIV1 is an ODD INTEGER then, Z equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1 + 0.5). If

PRU0_GPI_DIV0 is an INTEGER and PRU0_GPI_DIV1 is a NON-INTEGER then, Z equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1

+ 0.5 × PRU0_GPI_DIV0). If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are NON-INTEGERS then, Z equals (PRU0_GPI_DIV0 ×

PRU0_GPI_DIV1 + 0.25 × PRU0_GPI_DIV0).

(3)

The Y parameter is defined as follows: If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are INTEGERS -or- if PRU0_GPI_DIV0 is a NON-

INTEGER and PRU0_GPI_DIV1 is an EVEN INTEGER then, Y equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1). If PRU0_GPI_DIV0

is a NON-INTEGER and PRU0_GPI_DIV1 is an ODD INTEGER then, Y equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1 - 0.5). If

PRU0_GPI_DIV0 is an INTEGER and PRU0_GPI_DIV1 is a NON-INTEGER then, Y equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1

- 0.5 × PRU0_GPI_DIV0). If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are NON-INTEGERS then, Y1 equals (PRU0_GPI_DIV0 ×

PRU0_GPI_DIV1 - 0.25 × PRU0_GPI_DIV0) and Y2 equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1 + 0.25 × PRU0_GPI_DIV0), where

Y1 is the first high pulse and Y2 is the second high pulse.

CLOCKOUT

DATAOUT

PRSO1

PRSO2H

PRSO3

SPRSP08_TIMING_PRU_06

PRSO2L

Figure 7-99. PRU_ICSSG PRU Shift Out Timing

7.9.5.21.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Modes Electrical Data and Timing

Table 7-71 presents PRU Sigma Delta and Peripheral timing conditions.

Table 7-71. PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

V/ns

OUTPUT CONDITIONS

Output load capacitance

7.9.5.21.1.4.1 PRU_ICSSG PRU Timing Requirements - Sigma Delta Mode

NO.

MIN

MAX

UNIT

PRSD1

tc(SD_CLK)

Cycle time, SD_CLK

PRSD2L

tw(SD_CLKL)

Pulse Duration, SD_CLK Low

PRSD2H

tw(SD_CLKH)

Pulse Duration, SD_CLK High

PRSD3

tsu(SD_DATA-SD_CLK)

Setup time, SD_DATA valid before SD_CLK active edge

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AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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