SCIMX6QP4AVT2AB datasheet(158/160 Pages) NXP

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i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

158

NXP Semiconductors

Revision History

Table 90 provides a revision history for this i.MX 6DualPlus/6QuadPlus data sheet.

Table 90. i.MX 6DualPlus/6QuadPlus Data Sheet Document Revision History

Rev.

Number

Date

Substantive Change(s)

10/2018 Rev. 3 changes include the following:

• Table 20, “XTALI and RTC_XTALI DC Parameters,” on page 38,

– Row: XTALI input leakage current at startup, IXTALI_STARTUP: Changed from “... driven 32KHz RTC

clock @ 1.1V” to “...driven 24 MHz clock at 1.1V.”

• Table 47, “eMMC4.4/4.41 Interface Timing Specification,” on page 79,

– Row: SD2, uSDHC Output Delay: Changed tOD from 2.5 ns minimum to 2.8 ns and 7.1 ns maximum

to 6.8 ns.

11/2018 Rev. 2 changes include the following:

• Changed throughout: terminology from “floating” to “not connected”.

• Section 1, “Introduction” on page 1: Corrected A9 core speed from 1 GHz to 800 MHz.

• Figure 1, "Part Number Nomenclature—i.MX 6DualPlus and i.MX 6QuadPlus," on page 4: Corrected

Automotive grade frequency from 850 to 852 MHz.

• Section 1.2, “Features” on page 4: Changed Internal/external peripheral item from “LVDS serial ports—

One port up to 165 MPixels/sec…” to: “…—One port up to 170 MPixels/sec…”.

• Table 4, “Absolute Maximum Ratings,” on page 20: Multiple changes:

– Core supply voltages: Separated rows by LDO enabled and LDO bypass.

– Renamed Internal supply voltages to Core supply output voltage (LDO enabled) and changed

maximum value from 1.3 to 1.4V. Added symbol NVCC_PLL_OUT.

– Reordered VDD_HIGH_IN row and changed maximum value from 3.6 to 3.7V.

– DDR I/O supply voltage: added symbol, NVCC_DRAM, and footnote.

– GPIO I/O supply voltage: Added symbols. Changed maximum value from 3.6 to 3.7V.

– Added HDMI, PCIe, and SATA PHY (VPH and VP) supply voltage rows and values.

– Consolidated LVDS, MLB, and MIPI I/O supply voltage rows. Added symbols.

– Added rows: PCIe PHY, RGMII I/O, and SMVS IN supply voltages, symbols, and values.

– USB I/O supply voltage: moved symbols from parameters to symbol column. Changed maximum value

from 3.63 to 3.73V. Added symbol USB_OTG_CHD_B

– USB VBUS supply voltage: Changed maximum value from 5.25 to 5.35V.

– Separated Vin/Vout input/output voltage range distinguishing between non-DDR and DDR pins.

Changed maximum value for Vin/Vout input/output voltage range DDR pins to OVDD+0.4. Added

footnotes to both maximum values.

– Separated ESD immunity by HBM and CDM. Expanded symbols for each.

• Section 4.1.2, “Thermal Resistance” on page 21: Added NOTE: “Per JEDEC JESD51-2, the intent of

thermal resistance measurements…”.

• Table 5, “FCPBGA Package Thermal Resistance Data (Lidded),” on page 21: Added Lidded Table.

• Section 4.2.1, “Power-Up Sequence” on page 32:

– Removed inference to internal POR.

• Section 4.5.2, “OSC32K” on page 36: Removed content about calculating the proper current limiting

resistor for a coin cell.

• Section 4.6.1, “XTALI and RTC_XTALI (Clock Inputs) DC Parameters” on page 38: Added “NOTE: The

Vil and Vih specifications only apply when an external clock source is used…”.

• Table 20, “XTALI and RTC_XTALI DC Parameters,” on page 38: Added footnote to RTC_XTALI high level

DC input voltage row: “This voltage specification must not be exceeded and …”.

(Revision History table continued on next page.)

SCIMX6QP4AVT2AB Datasheet(PDF) 158 Page - NXP Semiconductors

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