SH7041A datasheet(379/923 Pages) RENESAS

379 / 923 page

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100% Duty Cycle: Figure 12.28 shows an example of a 100% duty cycle PWM waveform output

in PWM mode.

In PWM mode, when setting cycle = duty cycle the output waveform does not change, nor is there

a change of waveform for the first pulse immediately after clearing the counter.

TGRA

TCNT value

TGRB rewrite

TGRB

TIOCA

Time

100% duty cycle

Output does not change if period register and duty

cycle register compare matches occur simultaneously

Output does not change if period register and duty

cycle register compare matches occur simultaneously

TGRB rewrite

TGRA

TCNT

value

TGRB

rewrite

TGRB

rewrite

100%

duty cycle

TGRB

rewrite

Figure 12.28 PWM Mode Operation Example (100% Duty Cycle)

12.4.7

Phase Counting Mode

The phase counting mode detects the phase differential of two external clock inputs and counts the

TCNT counter up or down. This mode can be set for channels 1 and 2.

When set in the phase counting mode, an external clock is selected for the counter input clock,

regardless of the settings of the TPSC2–TPSC0 bits of TCR or the CKEG1 and CKEG0 bits.

TCNT also becomes an up/down counter. Since the TCR CCLR1/CCLR0 bits, TIOR, TIER, and

TGR functions are all enabled, input capture and compare-match functions and interrupt sources

can be used.

When the TCNT counter is incrementing, an overflow sets the TSR register TCFV (overflow

flag). When it is decrementing, an underflow sets the TCFU (underflow flag).

SH7041A Datasheet(PDF) 379 Page - Renesas Technology Corp