SH7041A datasheet(448/923 Pages) RENESAS

448 / 923 page

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Note that for channel 0, the TIOCC pin allows both default output setting by TIOR and PWM

output when setting buffer operation only for the TGRD register in PWM mode.

When using channel 0 in PWM mode 1 and setting buffer operation, use both the TGRC and

TGRD registers as buffer registers.

12.7.22

Cautions on Restarting with Sync Clear of Another Channel in Complementary

PWM Mode (A Mask Excluded)

The complementation PWM mode operates while waiting for the current, next and the following

set values as values of the PWM duty. If clearing sync from another channel during operation, the

PWM output will return to the default output and restart.

When restarting with sync clear, the following operations may occur:

1.When restarting with sync clear, the next set value is used for the PWM duty, however, the

following set value may be used by mistake.

2. If sync clear and the setting of the value following the next value of PWM duty (write to

TGR4D) occurs at the same time, the next set value may be overwritten.

How to avoid 1

When selecting the mode to transfer using the crest/trough in the complementary PWM transfer

mode, set the value following the next value of the PWM duty (write to TGR4D) while the

temporary register is not executing comparisons. Furthermore, set the occurrence timing of sync

clear while the temporary register is not executing comparisons.

When selecting the mode to transfer using the crest in the transfer mode, set the value following

the next value of the PWM duty (write to TGR4D) while the temporary register is not executing

comparisons and while TCNT3 and TCNT4 are counting up. Furthermore, set the occurrence

timing of sync clear while the temporary register is not executing comparisons and while TCNT3

and TCNT4 are counting up.

When selecting the mode to transfer using the trough in the transfer mode, set the value following

the next value of the PWM duty (write to TGR4D) while the temporary register is not executing

comparisons and while TCNT3 and TCNT4 are counting down. Furthermore, set the occurrence

timing of sync clear while the temporary register is not executing comparisons and while TCNT3

and TCNT4 are counting down.

How to avoid 2

Regardless of the transfer mode, set so that the sync clear and the setting of the value following

the next value (write to TGR4D) does not occur at the same time.

SH7041A Datasheet(PDF) 448 Page - Renesas Technology Corp