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SH7041A Datasheet(PDF) 512 Page - Renesas Technology Corp

Part # SH7041A
Description  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A Datasheet(HTML) 512 Page - Renesas Technology Corp

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474
• Bit 7—Communication Mode (C/A): Selects whether the SCI operates in the asynchronous or
clock synchronous mode.
Bit 7: C/
A
Description
0
Asynchronous mode (initial value)
1
Clocked synchronous mode
• Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in the asynchronous mode. In the
clock synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Bit 6: CHR
Description
0
Eight-bit data (initial value)
1
Seven-bit data. (When 7-bit data is selected, the MSB (bit 7) of the
transmit data register is not transmitted.)
• Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data, in the asynchronous mode. In the clock synchronous mode, a parity bit is
neither added nor checked, regardless of the PE setting.
Bit 5: PE
Description
0
Parity bit not added or checked (initial value)
1
Parity bit added and checked. When PE is set to 1, an even or odd
parity bit is added to transmit data, depending on the parity mode (O/
E)
setting. Receive data parity is checked according to the even/odd (O/
E)
mode setting.
• Bit 4—Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked.
The O/
E setting is used only in asynchronous mode and only when the parity enable bit (PE) is
set to 1 to enable parity addition and check. The O/
E setting is ignored in the clock
synchronous mode, or in the asynchronous mode when parity addition and check is disabled.
Bit 4: O/
E
Description
0
Even parity (initial value). If even parity is selected, the parity bit is
added to transmit data to make an even number of 1s in the transmitted
character and parity bit combined. Receive data is checked to see if it
has an even number of 1s in the received character and parity bit
combined.
1
Odd parity. If odd parity is selected, the parity bit is added to transmit
data to make an odd number of 1s in the transmitted character and
parity bit combined. Receive data is checked to see if it has an odd
number of 1s in the received character and parity bit combined.



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