SH7041A datasheet(681/923 Pages) RENESAS

681 / 923 page

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• Bits 5 and 4—PE2 Mode 1, 0 (PE2MD1 and PE2MD0): These bits select the function of the

PE2/TIOC0C/

DREQ1 pin.

Bit 5:

PE2MD1

Bit 4:

PE2MD0

Description

General input/output (PE2) (initial value)

MTU input capture input/output compare output (TIOC0C)

DREQ1 request receive input (PE2 in single chip mode)

Reserved

• Bits 3 and 2—PE1 Mode 1, 0 (PE1MD1 and PE1MD0): These bits select the function of the

PE1/TIOC0B/DRAK0 pin.

Bit 3:

PE1MD1

Bit 2:

PE1MD0

Description

General input/output (PE1) (initial value)

MTU input capture input/output compare output (TIOC0B)

DREQ0 request received output (DRAK0) (PE1 in single chip

mode)

Reserved

• Bits 1 and 0—PE0 Mode 1, 0 (PE0MD1 and PE0MD0): These bits select the function of the

PE0/TIOC0A/

DREQ0 pin.

Bit 1:

PE0MD1

Bit 0:

PE0MD0

Description

General input/output (PE0) (initial value)

MTU input capture input/output compare output (TIOC0A)

DREQ0 request receive input (PE0 in single chip mode)

Reserved

18.3.15

IRQOUT Function Control Register (IFCR)

The IFCR is a 16-bit read/write register used to control output when the multiplexed pins are

established as

IRQOUT outputs by the port D control register (PDCRH1) or port E control register

(PECR1). When PDCRH1 or PECR1 are set for any other function, the settings of this register

have no effect on the pin functions.

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