SH7041A datasheet(701/923 Pages) RENESAS

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19.7

Port F

Port F is an 8-pin input port. All modes are configured in the following way:

• PF7 (input)/AN7 (input)

• PF6 (input)/AN6 (input)

• PF5 (input)/AN5 (input)

• PF4 (input)/AN4 (input)

• PF3 (input)/AN3 (input)

• PF2 (input)/AN2 (input)

• PF1 (input)/AN1 (input)

• PF0 (input)/AN0 (input)

19.7.1

Table 19.18 summarizes the port F register.

Table 19.18 Port F Register

Name

Abbreviation

R/W

Initial Value

Address

Access Size

Port F data register

PFDR

External pin

dependent

H'FFFF83B3

19.7.2

Port F Data Register (PFDR)

PFDR is an 8-bit read-only register that stores data for port F. The bits PF7DR–PF0DR

correspond to the PF7/AN7–PF0/AN0 pins. There are no bits 15–8, so always access as eight bits.

Any value written into these bits is ignored, and there is no effect on the status of the pins. When

any of the bits are read, the pin status rather than the bit value is read directly. However, when an

A/D converter analog input is being sampled, values of 1 are read out. Table 19.19 shows the

read/write operations of the port F data register.

PFDR is not initialized by power-on resets, manual resets, standby mode, or sleep mode (the bits

always reflect the pin status).

Bit:

PF7DR

PF6DR

PF5DR

PF4DR

PF3DR

PF2DR

PF1DR

PF0DR

Initial value:

***

R/W:

Note: * Initial values are dependent on the status of the pins at the time of the reads.

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