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SH7041A Datasheet(PDF) 707 Page - Renesas Technology Corp |
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SH7041A Datasheet(HTML) 707 Page - Renesas Technology Corp |
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707 / 923 page ![]() 669 Section 21 128kB PROM 21.1 Overview This LSI has 128 kbytes of on-chip PROM.The on-chip ROM is connected to the CPU, the direct memory access controller (DMAC) and the data transfer controller (DTC) through a 32-bit data bus (figures 21.1). The CPU, DMAC, and DTC can access the on-chip ROM in 8, 16, and 32-bit widths. Data in the on-chip ROM can always be accessed in one cycle. H'00000000 H'00000004 H'00000001 H'00000005 H'00000002 H'00000006 H'00000003 H'00000007 H'0001FFFC H'0001FFFD H'0001FFFE H'0001FFFF On-chip ROM Internal data bus (32 bits) Figure 21.1 PROM Block Diagram The operating mode determines whether the on-chip ROM is valid or not. The operating mode is selected using mode-setting pins MD3–MD0 as shown in table 21.1. If you are using the on-chip ROM, select mode 2 or mode 3; if you are not, select mode 0 or 1. The on-chip ROM is allocated to addresses H'00000000–H'0001FFFF of memory area 0. |
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