SH7041A datasheet(744/923 Pages) RENESAS

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706

Set SWE bit in FLMCR1

= 1

m = 0

Write 32-byte data in reprogram data area

in RAM to flash memory consecutively

Start of programming

Store 32-byte program data in

reprogram data area

Read verify data

Clear SWE bit in FLMCR1

m = 1

End of programming

Program data = verify data?

End of 32-byte

data verification?

flag = 0?

Verify

Increment address

Programming failure

Clear SWE bit in FLMCR1

≥ 1000

← n + 1

Notes: *1 Data transfer is performed by byte transfer. The lower

8 bits of the first address written to must be H'00, H'20, H'40,

H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer

must be performed even if writing fewer than 32 bytes;

in this case, H'FF data must be written to the extra addresses.

*2 Verify data is read in 32-bit (longword) units.

*3 Even bits for which programming has been completed in a

32-byte programming loop will be subjected to additional

programming if they fail the subsequent verify operation.

*4 A 32-byte area for storing program data and a 32-byte area for

storing reprogram data are required in RAM. The contents of

the latter are rewritten according to the progress of the

programming operation.

*5 Make sure to set the wait times and repetitions as specified.

Programming may not complete correctly if values other than

the specified ones are used.

Start

RAM

Program data storage

area (32 bytes)

Reprogram data storage

area (32 bytes)

End of programming

Perform programming in the erased state.

Do not perform additional programming

on previously programmed addresses.

Write data (D)

Note: The memory erased state is 1. Programming is performed on 0 data.

Verify data (V) Rewrite data (X)

Comment

Programming completed

Programming incomplete; reprogram

Still in erased state; no action

Enable WDT

Disable WDT

Reprogram data computation

Transfer reprogram data to reprogram

data area

Wait 10

µs

Clear PV1(2) bit in FLMCR1(2)

Wait 4

µs

Dummy write of H'FF to verify address

Wait 2

µs

Set PV1(2) bit in FLMCR1(2)

Wait 4

µs

Clear PSU1(2) bit in FLMCR1(2)

Wait 10

µs

Clear P1(2) bit in FLMCR1(2)

Wait 10

µs

Set P1(2) bit in FLMCR1(2)

Wait 200

µs

Set PSU1(2) bit in FLMCR1(2)

Wait 50

µs

Figure 22.13 Program/Program Verify Flow

SH7041A Datasheet(PDF) 744 Page - Renesas Technology Corp

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