SH7041A datasheet(749/923 Pages) RENESAS

Part #	SH7041A

Description	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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749 / 923 page

711

MOV.L

#OK,R7

;

R7 <- OK (return value)

Program_end

.EQU

MOV.B

#H’00,R0

MOV.B

R0,@(FLMCR1,GBR)

;

Clear SWE

;

RTS

NOP

;

.ALIGN

PdataBuff

.RES.B

22.7.3

Erase Mode (n = 1 for Addresses H'0000–H'1FFFF, n = 2 for Addresses H'20000–

H'3FFFF)

When erasing flash memory, the erase/erase-verify flowchart shown in figure 22.14 should be

followed.

To perform data or program erasure, set the flash memory area to be erased in erase block register

n (EBRn) at least 10 µs after setting the SWE bit to 1 in flash memory control register 1

(FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program

runaway, etc. Set 5.3 µs as the WDT overflow period. After this, preparation for erase mode (erase

setup) is carried out by setting the ESUn bit in FLMCRn, and after the elapse of 200 µs or more,

the operating mode is switched to erase mode by setting the En bit in FLMCRn. The time during

which the En bit is set is the flash memory erase time. Set an erase time of 5 ms.

Note:

With flash memory erasing, preprogramming (setting all memory data in the memory to

be erased to all “0”) is not necessary before starting the erase procedure.

SH7041A Datasheet(PDF) 749 Page - Renesas Technology Corp