SH7041A datasheet(796/923 Pages) RENESAS

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Table 25.7

Bus Timing (Conditions: V

CC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ±

10%, AV

ref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = – 20 to +75°C)

Item

Symbol

Min

Max

Unit Figure

Write address setup time

—

25.8–25.9

Write address hold time

—

25.8, 25.9, 25.19

Write data hold time

WRH

0—

Read/write strobe delay time 1 t

RWD1

25.11–25.16

Read/write strobe delay time 2 t

RWD2

High-speed page mode CAS

precharge time

cyc – 25

—

25.16

RAS precharge time

cyc × (TPC + 1.5) – 15

—

25.11–25.16

CAS setup time

CSR

—

25.17, 25.18

AH delay time 1

AHD1

25.19

AH delay time 2

AHD2

Multiplex address delay time

MAD

Multiplex address hold time

MAH

0—

DACK delay time

DACKD1

25.8, 25.9, 25.11–

25.16, 25.19

Notes: n is the number of waits. m is 0 when the number of DRAM write cycle waits is 0, and 1

otherwise. RCD is the set value of the RCD bit in DCR. TPC is the set value of the TPC bit

in DCR.

*1 If the access time is satisfied, t

RDS need not be satisfied.

*2t

WDH (max) is a reference value.

*3 The delay time Min values are reference values (typ).

*4t

RDS is a reference value.

*5 When 28.7MHz, tASR=0ns (min)

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