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SH7041A Datasheet(PDF) 806 Page - Renesas Technology Corp |
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SH7041A Datasheet(HTML) 806 Page - Renesas Technology Corp |
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806 / 923 page ![]() 768 25.3.4 Direct Memory Access Controller Timing Table 25.8 Direct Memory Access Controller Timing (Conditions: V CC = 5.0 V ± 10%, AV CC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = – 20 to +75 °C) Item Symbol Min Max Unit Figure DREQ0 and DREQ1 setup time t DRQS 18 — ns 25.20 DREQ0 and DREQ1 hold time t DRQH 18 — ns DREQ0 and DREQ1 pulse width t DRQW 1.5 — t cyc 25.21 DRAK output delay time t DRAKD — 18 ns 25.22 CK tDRQS tDRQS tDRQS tDRQH DREQ0 DREQ1 Level clear DREQ0 DREQ1 Level DREQ0 DREQ1 Edge Figure 25.20 DREQ0 and DREQ1 Input Timing (1) |
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