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SH7041A Datasheet(PDF) 811 Page - Renesas Technology Corp |
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SH7041A Datasheet(HTML) 811 Page - Renesas Technology Corp |
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811 / 923 page  773 25.3.8 Serial Communication Interface Timing Table 25.12 Serial Communication Interface Timing (Conditions: V CC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AV CC = VCC ± 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = – 20 to +75 °C) Item Symbol Min Max Unit Figure Input clock cycle t scyc 4— t cyc 25.27 Input clock cycle (clock sync) t scyc 6— t cyc Input clock pulse width t sckw 0.4 0.6 t scyc Input clock rise time t sckr — 1.5 t cyc Input clock fall time t sckf — 1.5 t cyc Transmit data delay time (clock sync) t TXD — 100 ns 25.28 Receive data setup time (clock sync) t RXS 100 — ns Receive data hold time (clock sync) t RXH 100 — ns tsckw tsckr tsckf tscyc SCK0, SCK1 Figure 25.27 Input Clock Timing tscyc tTXD tRXS tRXH SCK0, SCK1 TXD0, TXD1 (Transmit data) RXD0, RXD1 (Receive data) Figure 25.28 SCI I/O Timing (Clock Sync Mode) |
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