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SH7041A Datasheet(PDF) 827 Page - Renesas Technology Corp |
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SH7041A Datasheet(HTML) 827 Page - Renesas Technology Corp |
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827 / 923 page  789 26.3.3 Bus Timing Table 26.6 Bus Timing (Conditions: V CC = 3.0 *1 to 3.6V, AV CC = 3.0 *1 to 3.6V, AV CC = VCC ± 10%, AV ref = 3.0 *1 to AV CC, VSS = AVSS = 0V, Ta = –20 to +75°C) Item Symbol Min Max Unit Figure Address delay time t AD 3*4 35 ns 26.8, 9, 11–16, 19 CS delay time 1 t CSD1 3*4 35 ns 26.8, 9, 19 CS delay time 2 t CSD2 3*4 35 ns Read strobe delay time 1 t RSD1 3*4 35 ns 26.8, 9, 11–16, 19 Read strobe delay time 2 t RSD2 3*4 35 ns Read data setup time t RDS *5 25 — ns Read data hold time t RDH 0— ns Write strobe delay time 1 t WSD1 3*4 35 ns Write strobe delay time 2 t WSD2 3*5 35 ns Write data delay time t WDD —45 ns Write data hold time t WDH 025*3 ns WAIT setup time t WTS 15 — ns 26.10,15, 19 WAIT hold time t WTH 0— ns RAS delay time 1 t RASD1 3*4 35 ns 26.11–18 RAS delay time 2 t RASD2 3*4 35 ns CAS delay time 1 t CASD1 3*4 35 ns CAS delay time 2 t CASD2 3*4 35 ns Read data access time t ACC *2 t cyc× (n+2) – 45 — ns 26.8, 9 Access time from read strobe t OE *2 t cyc× (n+1.5) – 40 — ns Access time from column address t AA *2 t cyc× (n+2) – 45 — ns 26.11–16 Access time from RAS t RAC *2 t cyc× (n+RCD+2.5) – 40 — ns Access time from CAS t CAC *2 t cyc× (n+1) – 40 — ns Row address hold time t RAH t cyc× (RCD+0.5) – 15 — ns Row address setup time t ASR 0— ns Data input setup time t DS t cyc× (m+0.5) – 27 — ns Data input hold time t DH 20 — ns Notes: n is the wait number. m is 1 unless the DRAM write cycle wait number is 0, then m is 0. RCD is the set value of the RCD bit of DCR. *1 SH7042/43 ZTAT (excluding A mask) are 3.2V. *2 If the access time is satisfied, then the t RDS need not be satisfied. *3t WDH (max) is a reference value. *4 The delay time min values are reference values (typ). *5t RDS is a reference value. |
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