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SH7041A Datasheet(PDF) 838 Page - Renesas Technology Corp |
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SH7041A Datasheet(HTML) 838 Page - Renesas Technology Corp |
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838 / 923 page ![]() 800 26.3.4 Direct Memory Access Controller Timing Table 26.8 Direct Memory Access Controller Timing (Conditions: V CC = 3.0 * to 3.6V, AV CC = 3.0* to 3.6V, AV CC = VCC ± 10%, AVref = 3.0 * to AV CC, VSS = AVSS = 0V, Ta = –20 to +75 °C) Item Symbol Min Max Unit Figure DREQ0, DREQ1 setup time t DRQS 35 — ns 26.20 DREQ0, DREQ1 hold time t DRQH 35 — ns DREQ0, DREQ1 pulse width t DRQW 1.5 — t cyc 26.21 DRAK output delay time t DRAKD — 35 ns 26.22 Note: * SH7042/43 ZTAT (excluding A mask) are 3.2V. CK tDRQS tDRQS tDRQS tDRQH DREQ0 DREQ1 Level clear DREQ0 DREQ1 Level DREQ0 DREQ1 Edge Figure 26.20 DREQ0 and DREQ1 Input Timing (1) |
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