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SH7041A Datasheet(PDF) 130 Page - Renesas Technology Corp

Part # SH7041A
Description  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A Datasheet(HTML) 130 Page - Renesas Technology Corp

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92
reset mode. (Keep at low level for at least the longest bus cycle.) See Appendix C, Pin States, for
the status of individual pins during manual reset mode.
In the manual reset status, manual reset exception processing starts when the
MRES pin is first
kept low for a set period of time and then returned to high. The CPU will then operate the same as
described for power-on resets.
5.3
Address Errors
Address errors occur when instructions are fetched or data read or written, as shown in table 5.6.
Table 5.6
Bus Cycles and Address Errors
Bus Cycle
Type
Bus
Master
Bus Cycle Description
Address Errors
Instruction
CPU
Instruction fetched from even address
None (normal)
fetch
Instruction fetched from odd address
Address error occurs
Instruction fetched from other than on-chip
peripheral module space*
None (normal)
Instruction fetched from on-chip peripheral module
space*
Address error occurs
Instruction fetched from external memory space
when in single chip mode
Address error occurs
Data
CPU or
Word data accessed from even address
None (normal)
read/write
DMAC
Word data accessed from odd address
Address error occurs
or DTC
Longword data accessed from a longword
boundary
None (normal)
Longword data accessed from other than a long-
word boundary
Address error occurs
Byte or word data accessed in on-chip peripheral
module space*
None (normal)
Longword data accessed in 16-bit on-chip
peripheral module space*
None (normal)
Longword data accessed in 8-bit on-chip peripheral
module space*
Address error occurs
External memory space accessed when in single
chip mode
Address error occurs
Note: * See section 10, Bus State Controller (BSC).



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