SH7041A datasheet(203/923 Pages) RENESAS

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10.1.3

Pin Configuration

Table 10.1 shows the bus state controller pin configuration.

Table 10.1

Pin Configuration

Signal

I/O

Description

A21–A0

Address output (A21–A18 will become input ports with power-on reset)

D31–D0

I/O

32-bit data bus. D15-D0 are address output and data I/O during address/data

multiplex I/O.

CS0–

CS3

Chip select

Strobe that indicates the read cycle for ordinary space/multiplex I/O. Also

output during DRAM access.

WRHH

Strobe that indicates a write cycle to the most significant byte (D31–D24) for

ordinary space/multiplex I/O. Also output during DRAM access.

WRHL

Strobe that indicates a write cycle to the 2nd byte (D23–D16) for ordinary

space/multiplex I/O. Also output during DRAM access.

WRH

Strobe that indicates a write cycle to the 3rd byte (D15–D8) for ordinary

space/multiplex I/O. Also output during DRAM access.

WRL

Strobe that indicates a write cycle to the least significant byte (D7–D0) for

ordinary space/multiplex I/O. Also output during DRAM access.

RDWR

Strobe indicating a write cycle to DRAM (used for DRAM space)

RAS

RAS signal for DRAM (used for DRAM space)

CASHH

CAS signal when accessing the most significant byte (D31–D24) of DRAM

(used for DRAM space)

CASHL

CAS signal when accessing the 2nd byte (D23–D16) of DRAM (used for DRAM

space)

CASH

CAS signal when accessing the 3rd byte (D15–D8) of DRAM (used for DRAM

space)

CASL

CAS signal when accessing the least significant byte (D7–D0) of DRAM (used

for DRAM space)

Signal to hold the address during address/data multiplex

WAIT

Wait state request signal

BREQ

Bus release request input

BACK

Bus use enable output

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