SH7041A datasheet(212/923 Pages) RENESAS

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Bit 9 (IW01)

Bit 8 (IW00)

Description

No idle cycle after accessing CS0 space

Inserts one idle cycle

Inserts two idle cycles

Inserts three idle cycles

(initial value)

• Bits 7–4—Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The

continuous access idle specification makes insertions to clearly delineate the bus intervals by

once negating the

CSn signal when doing consecutive accesses of the same CS space. When a

write immediately follows a read, the number of idle cycles inserted is the larger of the two

values specified by IW and CW. Refer to section 10.6, Waits between Access Cycles, for

details.

CW3 specifies the continuous access idles for CS3 space; CW2 specifies the continuous access

idles for CS2 space; CW1 specifies the continuous access idles for CS1 space and CW0

specifies the continuous access idles for CS0 space.

Bit 7 (CW3)

Description

No CS3 space continuous access idle cycles

One CS3 space continuous access idle cycle (initial value)

Bit 6 (CW2)

Description

No CS2 space continuous access idle cycles

One CS2 space continuous access idle cycle (initial value)

Bit 5 (CW1)

Description

No CS1 space continuous access idle cycles

One CS1 space continuous access idle cycle (initial value)

Bit 4 (CW0)

Description

No CS0 space continuous access idle cycles

One CS0 space continuous access idle cycle (initial value)

SH7041A Datasheet(PDF) 212 Page - Renesas Technology Corp