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STM32H750VB Datasheet(PDF) 296 Page - STMicroelectronics |
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STM32H750VB Datasheet(HTML) 296 Page - STMicroelectronics |
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296 / 337 page ![]() Electrical characteristics (rev V) STM32H750VB STM32H750ZB STM32H750IB STM32H750XB 296/336 DS12556 Rev 6 Figure 98. USART timing diagram in Slave mode SPI interface characteristics Unless otherwise specified, the parameters given in Table 203 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 120: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load CL = 30 pF • Measurement points are done at CMOS levels: 0.5VDD • IO Compensation cell activated. • HSLV activated when VDD ≤ 2.7 V • VOS level set to VOS1 Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). MSv65387V1 NSS input CPHA=0 CPOL=0 CPHA=0 CPOL=1 TX output RX input tsu(RX) th(RX) tw(SCKL) tw(SCKH) tc(SCK) tr(SCK) th(NSS) tdis(TX) tsu(NSS) ta(TX) tv(TX) Next bits IN Last bit OUT First bit IN First bit OUT Next bits OUT th(TX) tf(SCK) Last bit IN |
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