SPC584BX datasheet(101/142 Pages) STMICROELECTRONICS

101 / 142 page

DS11701 Rev 4

101/142

SPC584Bx

Electrical characteristics

101

•

All output timing is worst case and includes the mismatching of rise and fall times of the

output pads.

•

Output parameters are valid for CL = 25 pF, where CL is the external load to the device

(lumped). The internal package capacitance is accounted for, and does not need to be

subtracted from the 25 pF value.

•

Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may

reduce operating speeds and may cause incorrect operation.

•

Programming the IBFD register (I2C bus Frequency Divider) with the maximum

frequency results in the minimum output timings listed. The I2C interface is designed to scale

the data transition time, moving it to the middle of the SCL low period. The actual position is

affected by the pre-scale and division values programmed in the IBC field of the IBFD

Figure 42. I2C input/output timing

Table 59. I2C output timing specifications — SCL and SDA

No. Symbol C

Parameter

Value

Unit

Min

Max

— CC D Start condition hold time

—

PER_CLK

Cycle(1)

— CC D Clock low time

—

PER_CLK Cycle

— CC D Bus free time between Start and Stop condition

4.7

—

µs

— CC D Data hold time

—

PER_CLK Cycle

— CC D Clock high time

—

PER_CLK Cycle

— CC D Data setup time

—

PER_CLK Cycle

— CC D Start condition setup time (for repeated start condition only)

—

PER_CLK Cycle

— CC D Stop condition setup time

—

PER_CLK Cycle

1. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the

device reference manual for more detail.

SCL

SDA

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