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STM32F407IG Datasheet(PDF) 200 Page - STMicroelectronics |
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STM32F407IG Datasheet(HTML) 200 Page - STMicroelectronics |
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200 / 201 page ![]() Revision history STM32F405xx, STM32F407xx 200/201 DocID022152 Rev 6 19-Oct-2015 6 In the whole document, updated notes related to values guaranteed by design or by characterization. Updated Table 34: HSI oscillator characteristics. Changed fVCO_OUT minimum value and VCO freq to 100 MHz in Table 36: Main PLL characteristics and Table 37: PLLI2S (audio PLL) characteristics. Updated Figure 39: SPI timing diagram - slave mode and CPHA = 0. Updated Figure 53: 12-bit buffered /non-buffered DAC. Removed note 1 related to better performance using a restricted VDD range in Table 68: ADC accuracy at fADC = 30 MHz. Upated Figure 84: LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline. Updated Figure 87: UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline and Table 95: UFBGA176+25 - 201-ball, 10 × 10 × 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data Table 100. Document revision history (continued) Date Revision Changes |
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