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AM6548 Datasheet(PDF) 235 Page - Texas Instruments |
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AM6548 Datasheet(HTML) 235 Page - Texas Instruments |
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235 / 284 page  NO. MIN MAX UNIT PRIEP3 tsu(EDIO_DATA_IN- EDC_SYNCx_OUT) Setup time, EDIO_DATA_IN valid before EDC_SYNCx_OUT active edge 20 ns PRIEP4 th(EDC_SYNCx_OUT- EDIO_DATA_IN) Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT active edge 20 ns (1) P = PRU-ICSS IEP clock source period. EDC_SYNCx_OUT PRIEP4 PRIEP2 PRIEP3 EDIO_DATA_IN[7:0] SPRSP08_TIMING_PRU_IEP_01 PRIEP1 Figure 7-105. PRU_ICSSG PRU IEP SYNCx Timing 7.9.5.21.3.1.2 PRU_ICSSG IEP Timing Requirements - Digital IOs NO. MIN MAX UNIT IEPIO1 tw(EDIO_OUTVALIDL) Pulse Duration, EDIO_OUTVALID Low -2+14×P (1) ns IEPIO2 tw(EDIO_OUTVALIDH) Pulse Duration, EDIO_OUTVALID High -2+32×P (1) ns IEPIO3 td(EDIO_OUTVALID- EDIO_DATA_OUT) Delay time, EDIO_OUTVALID to EDIO_DATA_OUT 0 0+18×P (1) ns IEPIO4 tsk(EDIO_DATA_OUT) EDIO_DATA_OUT skew 5 ns (1) P = PRU-ICSS IEP clock source period. EDIO_DATA_OUT SPRSP08_TIMING_PRU_EDIO_DATA_OUT IEPIO4 Figure 7-106. PRU_ICSSG PRU IEP Digital IOs Timing 7.9.5.21.3.1.3 PRU_ICSSG IEP Timing Requirements - LATCHx_IN NO. MIN MAX UNIT PRLA1 tw(EDC_LATCHx_INL) Pulse Duration, EDC_LATCHx_IN Low 2+3×P(1) ns PRLA2 tw(EDC_LATCHx_INH) Pulse Duration, EDC_LATCHx_IN High 2+3×P (1) ns (1) P = PRU-ICSS IEP clock source period. EDC_LATCHx_IN PRLA2 SPRSP08_TIMING_PRU_IEP_02 PRLA1 Figure 7-107. PRU_ICSSG PRU IEP LATCHx_IN Timing www.ti.com AM6548, AM6528, AM6546, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 235 Product Folder Links: AM6548 AM6528 AM6546 AM6526 |
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