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STM32H753II Datasheet(PDF) 305 Page - STMicroelectronics |
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STM32H753II Datasheet(HTML) 305 Page - STMicroelectronics |
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305 / 361 page ![]() DS12117 Rev 8 305/360 STM32H753xI Electrical characteristics (rev V) 318 Figure 104. SPI timing diagram - master mode(1) 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. I2S Interface characteristics Unless otherwise specified, the parameters given in Table 205 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 121: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load CL = 30 pF • Measurement points are done at CMOS levels: 0.5VDD • IO Compensation cell activated. • HSLV activated when VDD ≤ 2.7 V • VOS level set to VOS1 Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (CK,SD,WS). ai14136c CPHA= 0 MOSI OUTPUT MISO INP UT CPHA= 0 LSB OUT LSB IN CPOL=0 CPOL=1 B I T1 OUT NSS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(MI) High CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(MI) tv(MO) th(MO) MSB IN BIT6 IN MSB OUT |
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