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Interrupts and Exception Handling

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

5-21

5.8.2

Interrupt Classes

All interrupts may be categorized as asynchronous/synchronous and critical/noncritical.

•

Asynchronous interrupts (such as machine check, critical input, and external interrupts) are

caused by events that are independent of instruction execution. For asynchronous

interrupts, the address reported in a save/restore register is the address of the instruction that

would have executed next had the asynchronous interrupt not occurred.

•

Synchronous interrupts are those that are caused directly by the execution or attempted

execution of instructions. Synchronous inputs may be either precise or imprecise, which are

described as follows:

— Synchronous precise interrupts are those that precisely indicate the address of the

instruction causing the exception that generated the interrupt or, in some cases, the

address of the immediately following instruction. The interrupt type and status bits

indicate which instruction is addressed in the appropriate save/restore register.

— Synchronous imprecise interrupts are those that may indicate the address of the

exception causing the exception that generated the interrupt, or some instruction after

the instruction causing the interrupt. If the interrupt was caused by either the context

synchronizing mechanism or the execution synchronizing mechanism, the address in

the appropriate save/restore register is the address of the interrupt forcing instruction. If

the interrupt was not caused by either of those mechanisms, the address in the

save/restore register is the last instruction to start execution and may not have

completed. No instruction following the instruction in the save/restore register has

executed.

5.8.3

Interrupt Types

The e500 core processes all interrupts as either machine check, critical, or noncritical types.

Separate control and status register sets are provided for each interrupt type. The core handles

interrupts from these three types in the following priority order:

1. Machine check interrupt (highest priority)—The e500 defines a separate set of resources

for the machine check interrupt. They use the machine check save and restore registers

(MCSRR0/MCSRR1) to save state when they are taken, and they use the rfmci instruction

to restore state. These interrupts can be masked by the machine check enable bit,

MSR[ME].

2. Noncritical interrupts—First-level interrupts that allow the processor to change program

flow to handle conditions generated by external signals, errors, or unusual conditions

arising from program execution or from programmable timer-related events. These

interrupts are largely identical to those previously defined by the OEA portion of the

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