MPC8540 datasheet(240/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

5-26

Freescale Semiconductor

Core Complex Overview

•

Hardware partially managed by L2 MMU

•

Supports snooping of TLBs by both internal and external tlbivax instructions

The level-2 MMU has the following features:

•

A 16-entry, fully associative L2 TLB array (TLB1) that supports all nine page sizes

•

256-entry, 2-way set-associative TLB array (TLB0) that supports only 4-Kbyte pages

•

Hardware assist for TLB miss exceptions

•

Software managed by tlbre, tlbwe, tlbsx, tlbsync, tlbivax, and mtspr instructions

•

Supports snooping of TLB by both internal and external tlbivax instructions

5.9.1

Address Translation

The core complex fetch and load/store units generate 32-bit effective addresses. The MMU

translates these addresses to real 32-bit addresses (which are used for memory bus accesses) using

an interim 41-bit virtual address. Figure 5-8 shows the translation flow.

Figure 5-8. Effective-to-Real Address Translation Flow

The appropriate L1 MMU (instruction or data) is checked for a matching address translation. The

instruction L1 MMU and data L1 MMU operate independently and can be accessed in parallel, so

that hits for instruction accesses and data accesses can occur in the same clock. If an L1 MMU

misses, the request for translation is forwarded to the unified (instruction and data) L2 MMU. If

found, the contents of the TLB entry are concatenated with the byte address to obtain the physical

address of the requested access. On misses, the L1 TLB entries are replaced from their L2 TLB

counterparts using a true LRU algorithm.

Effective Page Number

Byte Address

Real Page Number

Byte Address

32-bit Effective Address (EA)

32-bit Real Address

15–20 Bits*

>12 Bits*

15–20 Bits*

>12 Bits*

Three 41-bit Virtual Addresses (VAs)

L1 MMUs

Instruction L1 MMU

Data L1 MMU

2 TLBs

* Number of bits depends on page size (4 Kbytes–128 Mbytes)

8 bits

PID0

PID1

PID2

L2 MMU (Unified)

16-Entry Fully-Assoc. VSP Array (TLB1)

256-Entry 2-Way Set Assoc. Array (TLB0)

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