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PowerQUICC III Implementation Details

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

5-33

the Book E reset definition, the EIS and the e500 define specific aspects of the MMU page

translation and protection mechanisms. Unlike the AIM version of the PowerPC core, as soon as

instruction fetching begins, the e500 core is in virtual mode with a hardware-initialized TLB entry.

5.13.6 Little-Endian Mode

Unlike the AIM version of the PowerPC architecture, where little-endian mode is controlled on a

system basis, Book E allows control of byte ordering on a memory page basis. In addition, the

little-endian mode used in Book E is true little endian.

5.14 PowerQUICC III Implementation Details

Table 5-8 summarizes e500 core functionality that is not implemented by PowerQUICC III

devices.

Table 5-8. Differences Between the e500 Core and the PowerQUICC III Core

Implementation

Feature

PowerQUICC Implementation

Cache protocol

The L2 cache does not support MESI cache protocol.

Multiprocessor

functionality

Because PowerQUICC III is designed for a uniprocessor environment, the following e500 functionality is not

implemented:

• The memory coherence bit, M, which is controlled through MAS2[M] and MAS4[MD] has no effect.

• HID1[ABE] has meaning only in that it must be set to ensure that cache and TLB management instructions

operate properly with respect to the L2 cache.

• Dynamic snooping does not occur in power-stopped state (see the note below in the entry for dynamic bus

snooping).

Nexus support

Nexus is not supported. The Nexus processor ID register (NPIDR) and the Nexus bus enable bit

(HID1[NEXEN]) are not supported.

R1 and R2 data

bus parity

R1 and R2 data bus parity are disabled on PowerQUICC III devices. HID1[R1DPE,R2DPE] are reserved.

Dynamic bus

snooping

The PowerQUICC III devices do not perform dynamic bus snooping as described here. That is, when the e500

core is in core-stopped state (which is the state of the core when the PowerQUICC III devices is in either the

nap or sleep state), the core is not awakened to perform snoops on global transactions. Therefore, before

entering nap or sleep modes, L1 caches should be flushed if coherency is required during these power-down

modes. For more information, see Section 18.5.1.9, “Snooping in Power-Down Modes.”

Supported

TCR[WRC]

PowerQUICC III devices define values for 01, 10, and 11, as follows:

00 No watchdog timer reset can occur.

01 Force processor checkstop on second timeout of watchdog timer

10 Assert processor reset output (core_hreset_req) on second timeout of watchdog timer

11 Reserved

SPE and SPFP

APUs

The SPE and SPFP APU functionality will not be implemented in next generation of PowerQUICC devices.

Freescale Semiconductor strongly recommends that use of these instructions be confined to libraries and

device drivers. Customer software that uses SPE or SPFP instructions at the assembly level or that uses SPE

or SPFP intrinsics will require rewriting for upward compatibility with next generation PowerQUICC devices.

Freescale Semiconductor offers a libmoto_e500 library that uses SPE and SPFP APU instructions. Freescale

Semiconductor will also provide future libraries to support next generation PowerQUICC devices.

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