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ST72361 Datasheet(PDF) 202 Page - STMicroelectronics |
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ST72361 Datasheet(HTML) 202 Page - STMicroelectronics |
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202 / 224 page  ST72361 202/224 12.12 COMMUNICATION INTERFACE CHARACTERISTICS 12.12.1 SPI - Serial Peripheral Interface Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Figure 116. SPI Slave Timing Diagram with CPHA = 03) Notes: 1. Data based on design simulation and/or characterization results, not tested in production. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 3. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD. 4. Depends on fCPU. For example, if fCPU = 8 MHz, then TCPU = 1 / fCPU = 125ns and tsu(SS) = 550ns. Symbol Parameter Conditions Min Max Unit fSCK = 1 / tc(SCK) SPI clock frequency Master, fCPU = 8 MHz fCPU / 128 = 0.0625 fCPU / 4 = 2 MHz Slave, fCPU = 8 MHz 0 fCPU / 2 = 4 tr(SCK) SPI clock rise and fall time See I/O port pin description tf(SCK) tsu(SS) 1) SS setup time4) Slave (4 x TCPU) + 50 ns th(SS) 1) SS hold time 120 tw(SCKH) 1) SCK high and low time Master 100 tw(SCKL) 1) Slave 90 tsu(MI) 1) Data input setup time Master 100 tsu(SI) 1) Slave th(MI) 1) Data input hold time Master th(SI) 1) Slave ta(SO) 1) Data output access time Slave 0 120 tdis(SO) 1) Data output disable time 240 tv(SO) 1) Data output valid time Slave (after enable edge) 90 th(SO) 1) Data output hold time 0 tv(MO) 1) Data output valid time Master (after enable edge) 120 th(MO) 1) Data output hold time 0 SS INPUT CPHA = 0 MOSI INPUT MISO OUTPUT CPHA = 0 tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tv(SO) ta(SO) tsu(SI) th(SI) MSB OUT MSB IN BIT6 OUT LSB IN LSB OUT Seenote2 CPOL = 0 CPOL = 1 tsu(SS) th(SS) tdis(SO) th(SO) See note 2 BIT1 IN |
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