STM32L151CB-A datasheet(128/130 Pages) STMICROELECTRONICS

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Revision history

STM32L151x6/8/B-A STM32L152x6/8/B-A

128/130

DocID024330 Rev 5

25-Apr-2016

Updated Section 7: Package information structure: Paragraph titles

and paragraph heading level.

Updated Section 7: Package information for all package device

markings, adding text for device orientation versus pin 1/ ball A1

identifier.

Updated Figure 32: LQFP100 14 x 14 mm, 100-pin package top

view example removing gate mark.

Updated Table 65: LQFP64 10 x 10 mm, 64-pin low-profile quad flat

package mechanical data.

Updated Section 7.5: UFBGA100 7 x 7 mm, 0.5 mm pitch, ultra thin

fine-pitch ball grid array package information adding Table 69:

UFBGA100 7 x 7 mm, 0.5 mm pitch, recommended PCB design

rules and Figure 43: UFBGA100 7 x 7 mm, 0.5 mm pitch, ultra thin

fine-pitch ball grid array package recommended footprint.

Updated Section 7.6: TFBGA64 5 x 5 mm, 0.5 mm pitch, thin fine-

pitch ball grid array package information adding Table 71: TFBGA64

5 x 5 mm, 0.5 mm pitch, recommended PCB design rules and

changing Figure 46: TFBGA64, 5 x 5 mm, 0.5 mm pitch, thin fine-

pitch ball grid array package recommended footprint.

Updated Table 17: Embedded internal reference voltage

temperature coefficient at 100ppm/°C and table note 3: “guaranteed

by design” changed by “guaranteed by characterization results”.

Updated Table 62: Comparator 2 characteristics new maximum

threshold voltage temperature coefficient at 100ppm/°C.

Updated Table 40: ESD absolute maximum ratings CDM class.

Updated all the notes, removing ‘not tested in production’.

Updated Table 11: Voltage characteristics adding note about VREF-

pin.

Updated Table 3: Functionalities depending on the operating power

supply range LSI and LSE functionalities putting “Y” in Standby

mode.

Removed note 1 below Figure 2: Clock tree.

Updated Table 58: DAC characteristics resistive load.

Table 74. Document revision history (continued)

Date

Revision

Changes

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