ST72324B datasheet(133/167 Pages) STMICROELECTRONICS

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ST72324B

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12.9 I/O PORT PIN CHARACTERISTICS

12.9.1 General Characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specifica-

tion. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. Refer to Section 12.2.2

on page 116 for more details.

4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see Figure 66). Cur-

rent peak value based on design simulation and technology characteristics, not tested in production, and depending on

VDD and temperature values.

5. The Schmitt trigger that is connected to every I/O port is disabled for analog inputs only when ADON bit is ON and the

particular ADC channel is selected (with port configured in input floating mode)". When the ADON bit OFF static current

consumption is induced.

6. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-

scribed in Figure 67).

7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage (standard voltage

devices)1)

0.3xVDD

VIH

Input high level voltage 1)

0.7xVDD

Vhys

Schmitt trigger voltage hysteresis 2)

0.7

IINJ(PIN)

Injected Current on Flash device pin PB0

VDD=5V

0+4

Injected Current on other I/O pins

±4

ΣIINJ(PIN)3)

Total injected current (sum of all I/O and

control pins)

±25

Ilkg

Input leakage current

VSS ≤ VIN ≤ VDD

±1

µA

Static current consumption induced by each

floating input pin

Floating input

mode4)5)

200

RPU

Weak pull-up equivalent resistor 6)

VIN=VSS

VDD=5V

120

250

Ω

CIO

I/O pin capacitance

tf(IO)out

Output high to low level fall time 1)

CL=50pF

Between 10% and

90%

tr(IO)out

Output low to high level rise time 1)

tw(IT)in

External interrupt pulse time 7)

1tCPU

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