ST72324B datasheet(165/167 Pages) STMICROELECTRONICS

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ST72324B

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15.2 8/16K FLASH DEVICES ONLY

15.2.1 39-Pulse ICC Entry Mode

ICC mode entry using ST7 application clock (39

pulses) is not supported. External clock mode

must be used (36 pulses). Refer to the ST7 Flash

Programming Reference Manual.

15.3 32K FLASH DEVICES ONLY

15.3.1 ADC Accuracy in 32K Flash Devices

The ADC accuracy in 32K Flash Devices deviates

from table in Section 12.13.3 on page 146 as fol-

lows:

15.4 16K AND 8K ROM DEVICES ONLY

15.4.1 Read-Out Protection with LVD

Read-out protection is not supported if the LVD is

enabled.

15.4.2 I/O Port A and F Configuration

When using an external quartz crystal or ceramic

resonator, a few fOSC2 clock periods may be lost

when the signal pattern in Table 34 occurs . This is

because this pattern causes the device to enter

test mode and return to user mode after a few

clock periods. User program execution and I/O

status are not changed, only a few clock cycles are

lost.

This happens with either one of the following con-

figurations:

PA3=0, PF4=1, PF1=0 while PLL option is disa-

bled and PF0 is toggling

PA3=0, PF4=1, PF1=0, PF0=1 while PLL option is

enabled

This is detailed in the following table

Table 34. Port A and F Configuration:

As a consequence, for cycle-accurate operations,

these configurations are prohibited in either input

or output mode.

Workaround:

To avoid this occurring, it is recommended to con-

nect one of these pins to GND (PF4 or PF0) or

VDD (PA3 or PF1).

15.5 32K ROM DEVICES ONLY

The power consumption in Active Halt mode is

190µA typ. and 300µA max.

Symbol

Max2)

Unit

|ET|

LSB

|EO|

|EG|

4.5

|ED|

|EL|

PLL PA3 PF4 PF1

PF0

Clock

Disturbance

OFF

Tog-

gling

Max. 2 clock cy-

cles lost at each

rising or falling

edge of PF0

Max. 1 clock cycle

lost out of every 16

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